View M36W0R6050B1_226425.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M36W0R6050T1 M36W0R6050B1
64 Mbit (4 Mb x16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb x16) PSRAM, multi-chip package
Features
Multi-Chip Package - 1 die of 64 Mbit (4 Mb x 16) Flash memory - 1 die of 32 Mbit (2 Mb x 16) Pseudo SRAM Supply voltage - VDDF = VDDP = VDDQF = 1.7 V to 1.95 V Low power consumption Electronic signature - Manufacturer Code: 20h - Device code (top flash configuration), M36W0R6050T1: 8810h - Device code (bottom flash configuration), M36W0R6050B1: 8811h Package - ECOPACK(R)
FBGA

Stacked TFBGA88 (ZA)
Block locking - All blocks locked at Power-up - Any combination of blocks can be locked - WPF for Block Lock-Down Security - 128-bit user programmable OTP cells - 64-bit unique device number Common Flash Interface (CFI) 100 000 program/erase cycles per block
Flash memory
Programming time - 8 s by Word typical for Fast Factory Program - Double/Quadruple Word Program option - Enhanced Factory Program options Memory blocks - Multiple Bank memory array: 4 Mbit Banks - Parameter Blocks (Top or Bottom location) Synchronous / Asynchronous Read - Synchronous Burst Read mode: 66 MHz - Asynchronous/ Synchronous Page Read mode - Random Access: 70 ns Dual operations - Program Erase in one Bank while Read in others - No delay between Read and Write operations

PSRAM

Access time: 70 ns Asynchronous Page Read - Page size: 8 words - First access within page: 70 ns - Subsequent read within page: 20 ns Three Power-down modes - Deep Power-Down - Partial Array Refresh of 4 Mbits - Partial Array Refresh of 8 Mbits
November 2007
Rev 2
1/22
www.numonyx.com
1
Contents
M36W0R6050T1, M36W0R6050B1
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 Address inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data inputs/outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Chip Enable (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Write Protect (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Latch Enable (LF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Clock (KF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Wait (WAITF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PSRAM Chip Enable (E1P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PSRAM Chip Enable (E2P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VDDF supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VDDP supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VDDQF supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VPPF program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 4 5 6
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/22
M36W0R6050T1, M36W0R6050B1
Contents
7 8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/22
List of tables
M36W0R6050T1, M36W0R6050B1
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stacked TFBGA88 8 x 10 mm - 8 x 10 ball array, 0.8 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4/22
M36W0R6050T1, M36W0R6050B1
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stacked TFBGA88 8 x 10 mm - 8 x 10 active ball array, 0.8 mm pitch, package outline. . 18
5/22
Description
M36W0R6050T1, M36W0R6050B1
1
Description
The M36W0R6050T1 and M36W0R6050B1 combine two memories in a Multi-Chip Package:

a 64-Mbit, Multiple Bank Flash memory, the M58WR064HT/B, and a 32-Mbit Pseudo SRAM, the M69KB048BD.
The purpose of this document is to describe how the two memory components operate with respect to each other. It must be read in conjunction with the M58WR064HT/B and M69KB048BD datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. These datasheets are available from the Numonyx web site: www.numonyx.com. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8 x10 mm, 8 x 10 ball array, 0.8 mm pitch) package. It is supplied with all the bits erased (set to `1'). Figure 1. Logic diagram
VDDQF VDDF 22 A0-A21 DQ0-DQ15 EF GF WF RPF WPF LF KF E1P GP WP E2P UBP LBP M36W0R6050T1 M36W0R6050B1 WAITF VPPF VDDP 16
VSS
Ai12035
6/22
M36W0R6050T1, M36W0R6050B1 Table 1.
A0-A21
(1)
Description
Signal names
Address Inputs Common Data Inputs/Outputs Flash Memory Power Supply Flash memory Power Supply for I/O Buffers Common Flash Optional Supply Voltage for Fast Program & Erase Ground PSRAM Power Supply Not Connected Internally Do Not Use as Internally Connected
DQ0-DQ15 VDDF VDDQF VPPF VSS VDDP NC DU
Flash memory control functions LF EF GF WF RPF WPF KF WAITF PSRAM control functions E1P GP WP E2P UBP LBP Chip Enable input Output Enable input Write Enable input Power-down input Upper Byte Enable input Lower Byte Enable input Latch Enable input Chip Enable input Output Enable input Write Enable input Reset input Write Protect input Burst Clock Wait Data in Burst Mode
1. A21 is an address input for the Flash memory component only.
7/22
Description Figure 2. TFBGA connections (top view through package)
1 2 3 4 5 6
M36W0R6050T1, M36W0R6050B1
7
8
A
DU
DU
DU
DU
B
A4
A18
A19
VSS
VDDF
NC
A21
A11
C
A5
LBP
NC
VSS
NC
KF
NC
A12
D
A3
A17
NC
VPPF
WP
EP
A9
A13
E
A2
A7
NC
WPF
LF
A20
A10
A15
F
A1
A6
UBP
RPF
WF
A8
A14
A16
G
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAITF
NC
H
GP
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
NC
J
NC
GF
DQ9
DQ11
DQ4
DQ6
DQ15
VDDQF
K
EF
NC
NC
NC
VDDP
NC
VDDQF
E2P
L
VSS
VSS
VDDQF
VDDF
VSS
VSS
VSS
VSS
M
DU
DU
DU
DU
AI12037
8/22
M36W0R6050T1, M36W0R6050B1
Signal descriptions
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device.
2.1
Address inputs (A0-A21)
Addresses A0-A21 are common inputs for the Flash memory and PSRAM components, whereas A21 is an address input for the Flash memory component only. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Flash memory Program/Erase Controller, and they select the cells to access in the PSRAM.
2.2
Data inputs/outputs (DQ0-DQ15)
For the Flash memory, the Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation. For the PSRAM, the Upper Byte Data Inputs/Outputs carry the data to or from the upper part of the selected address during a Write or Read operation, when Upper Byte Enable (UBP) is driven Low. Likewise, the Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the selected address during a Write or Read operation, when Lower Byte Enable (LBP) is driven Low.
2.3
Flash Chip Enable (EF)
The Chip Enable inputs activate the memory control logics, input buffers, decoders and sense amplifiers. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level.
2.4
Flash Output Enable (GF)
The Output Enable pins control data outputs during Flash memory Bus Read operations.
2.5
Flash Write Enable (WF)
The Write Enable controls the Bus Write operation of the Flash memories' Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.
9/22
Signal descriptions
M36W0R6050T1, M36W0R6050B1
2.6
Flash Write Protect (WPF)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the LockedDown blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (Refer to Lock Status Table in M58WR064HT/B datasheet).
2.7
Flash Reset (RPF)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to the M58WR064HT/B datasheet, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to the M58WR064HT/B datasheet).
2.8
Flash Latch Enable (LF)
Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is Low, VIL, and it is inhibited when Latch Enable is High, VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported.
2.9
Flash Clock (KF)
The Clock input synchronizes the Flash memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is don't care during Asynchronous Read and in write operations.
2.10
Flash Wait (WAITF)
WAIT is a Flash output signal used during Synchronous Read to indicate whether the data on the output bus are valid. This output is high impedance when Flash Chip Enable is at VIH or Flash Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAITF signal is not gated by Output Enable.
2.11
PSRAM Chip Enable (E1P)
When asserted (Low), the Chip Enable, E1P, activates the memory state machine, address buffers and decoders, allowing Read and Write operations to be performed. When deasserted (High), all other pins are ignored, and the device is automatically put in Standby mode.
10/22
M36W0R6050T1, M36W0R6050B1
Signal descriptions
2.12
PSRAM Chip Enable (E2P)
When de-asserted (Low), the Chip Enable input E2P, puts the device in Power-Down mode. This is the lowest power mode according to the Configuration Register settings (see M69KB048BD datasheet).
2.13
PSRAM Output Enable (GP)
The Output Enable, GP, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus.
2.14
PSRAM Write Enable (WP)
The Write Enable, WP, controls the Bus Write operation of the memory's Command Interface.
2.15
PSRAM Upper Byte Enable (UBP)
The Upper Byte Enable, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8DQ15) to or from the upper part of the selected address during a Write or Read operation.
2.16
PSRAM Lower Byte Enable (LBP)
The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0DQ7) to or from the lower part of the selected address during a Write or Read operation.
2.17
VDDF supply voltage
VDDF provides the power supply to the internal core of the Flash memory component. It is the main power supplies for all Flash memory operations (Read, Program and Erase).
2.18
VDDP supply voltage
The VDDP Supply Voltage supplies the power for all operations (Read or Write) and for driving the refresh logic, even when the device is not being accessed.
2.19
VDDQF supply voltage
VDDQF provides the power supply for the Flash memory I/O pins. This allows all Outputs to be powered independently of the Flash memory core power supply, VDDF.
11/22
Signal descriptions
M36W0R6050T1, M36W0R6050B1
2.20
VPPF program supply voltage
VPPF is both a Flash Memory control input and a Flash Memory power supply pin. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQF) VPPF is seen as a control input. In this case a voltage lower than VPPLKF gives an absolute protection against Program or Erase, while VPPF > VPP1F enables these functions (see the M58WR064HT/B datasheet for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If VPPF is in the range of VPPHF it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed.
2.21
VSS ground
VSS is the common ground reference for all voltage measurements in the Flash memory (core and I/O Buffers) and PSRAM components.
Note:
Each Flash memory device in a system should have its supply voltages (VDDF, VDDQF) and the program supply voltage VPPF decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 5: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents.
12/22
M36W0R6050T1, M36W0R6050B1
Functional description
3
Functional description
The Flash memory and PSRAM components have separate power supplies but share the same grounds. They are distinguished by three Chip Enable inputs: EF for the Flash memory and E1P and E2P for the PSRAM. Recommended operating conditions do not allow more than one device to be active at a time. The most common example is simultaneous read operations on the Flash memory and the PSRAM which would result in a data bus contention. Therefore it is recommended to put the other devices in the high impedance state when reading the selected device. Figure 3. Functional block diagram
VDDF VPPF VDDQF
A21
EF GF WF LF KF RPF A0-A20 WPF
64 Mbit Flash Memory
WAITF
DQ0-DQ15
VDDP
E1P GP WP E2P UBP LBP 32 Mbit PSRAM
VSS
AI12.36
13/22
Functional description Table 2. Main operating modes
EF VIL VIL VIL GP VIL VIH X WP VIH VIL VIH LF VIL(2) VIL(2) VIL RPF WAITF(4) VIH VIH VIH E1P E2P
M36W0R6050T1, M36W0R6050B1
Operation Flash Read Flash Write Flash Address Latch Flash Output Disable Flash Standby Flash Reset PSRAM Read
GP
WP
UBP LBP
DQ15-DQ0 Flash Data Out
PSRAM must be disabled
Flash Data In Flash Data Out or Hi-Z
(3)
VIL VIH X
VIH X X
VIH X X
X X X
VIH VIH VIL Hi-Z Hi-Z VIL VIH VIH VIH VIH VIL VIL VIH VIH X X VIH VIL VIH X X VIL VIL X X X VIL VIL X X X Any PSRAM mode is allowed
Flash Hi-Z Flash Hi-Z Flash Hi-Z PSRAM data out PSRAM data in PSRAM Hi-Z PSRAM Hi-Z PSRAM Hi-Z
Flash Memory must be disabled PSRAM Write Output Disable PSRAM Standby PSRAM Deep Power-Down
1. X = Don't care. 2. LF can be tied to VIH if the valid address has been previously latched. 3. Depends on GF. 4. WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR064HT/B datasheet for details.
VIL VIL Any Flash mode is allowed. VIH X
14/22
M36W0R6050T1, M36W0R6050B1
Maximum rating
4
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 3.
Symbol TA TBIAS TSTG VIO VDDF VDDQF VDDP VPPF IO tVPPFH
Absolute maximum ratings
Value Parameter Min Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltage Flash Memory Core Supply Voltage Input/Output Supply Voltage PSRAM Supply Voltage Flash Memory Program Voltage Output Short Circuit Current Time for VPPF at VPPFH -30 -40 -55 -0.5 -0.2 -0.2 -0.5 -0.2 Max 85 125 125 VDDQF+0.6 2.45 2.45 3.6 14 100 100 C C C V V V V V mA hours Unit
15/22
DC and ac parameters
M36W0R6050T1, M36W0R6050B1
5
DC and ac parameters
This section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. The parameters in the dc and ac characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4: Operating and ac measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 4. Operating and ac measurement conditions
Flash memory Parameter Min VDDF Supply Voltage VDDP Supply Voltage VDDQF Supply Voltage
VPPF Supply Voltage (Factory environment) VPPF Supply Voltage (Application
PSRAM Unit Min - 1.7 - - - -30 50 Max - 1.95 - - - 85 V V V V V C pF ns 0 to VDDP VDDP/2 V V
Max 1.95 - 1.95 12.6 VDDQF +0.4 85 30 5
1.7 - 1.7 11.4 -0.4 -30
environment) Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
0 to VDDQF VDDQF/2
Figure 4.
AC measurement I/O waveform
VDDQF VDDQF/2 0V
AI12057
16/22
M36W0R6050T1, M36W0R6050B1 Figure 5. AC measurement load circuit
VDDQF
DC and ac parameters
VDDF
VDDQF 16.7k DEVICE UNDER TEST
0.1F 0.1F
CL
16.7k
CL includes JIG capacitance
AI12058
Table 5.
Symbol CIN COUT
Device capacitance
Parameter Input Capacitance Output Capacitance Test condition VIN = 0V VOUT = 0V Min Max 12 15 Unit pF pF
1. Sampled only, not 100% tested.
Please refer to the M58WR064HT/B and M69KB048BD datasheets for further dc and ac characteristics values and illustrations.
17/22
Package mechanical
M36W0R6050T1, M36W0R6050B1
6
Package mechanical
In order to meet environmental requirements, Numonyx offers the M36W0R6050T1 and M36W0R6050B1 devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 6. Stacked TFBGA88 8 x 10 mm - 8 x 10 active ball array, 0.8 mm pitch, package outline
D D1
e SE E E2 E1 b BALL "A1"
ddd FE FE1 A A1 FD SD A2
BGA-Z42
1. Drawing is not to scale.
18/22
M36W0R6050T1, M36W0R6050B1 Table 6.
Package mechanical
Stacked TFBGA88 8 x 10 mm - 8 x 10 ball array, 0.8 mm pitch, package mechanical data
millimeters inches Max 1.200 0.200 0.850 0.350 8.000 5.600 0.100 10.000 7.200 8.800 0.800 1.200 1.400 0.600 0.400 0.400 - - 9.900 10.100 0.3937 0.2835 0.3465 0.0315 0.0472 0.0551 0.0236 0.0157 0.0157 - - 0.3898 0.300 7.900 0.400 8.100 0.0335 0.0138 0.3150 0.2205 0.0039 0.3976 0.0118 0.3110 0.0157 0.3189 0.0079 Typ Min Max 0.0472
Symbol Typ A A1 A2 b D D1 ddd E E1 E2 e FD FE FE1 SD SE Min
19/22
Part numbering
M36W0R6050T1, M36W0R6050B1
7
Part numbering
Table 7.
Example: Device Type M36 = Multiple Memory Product (Multiple Flash + RAM) Flash 1 Architecture W = Multiple Bank, Burst mode Flash 2 Architecture 0 = none present Operating Voltage R = VDDF = VDDQF = VDDP = 1.7 V to 1.95 V Flash 1 Density 6 = 64 Mbit Flash 2 Density 0 = none present RAM 1 Density 5 = 32 Mbit RAM 0 Density 0 = none present Parameter Blocks Location T = Top Boot Block Flash B = Bottom Boot Block Flash Product Version 1 = 90 nm Flash technology, 70 ns; 0.13 m RAM, 70 ns speed Package ZAQ = Stacked TFBGA88 8 x 10 mm - 8 x 10 active ball array, 0.8 mm pitch Option E = ECOPACK(R) Package, Standard Packing F = ECOPACK(R) Package, Tape & Reel Packing
Ordering information scheme
M36 W 0 R 6 0 5 0 T 1 ZAQ E
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you.
20/22
M36W0R6050T1, M36W0R6050B1
Revision history
8
Revision history
Table 8.
Date 06-Dec-2005 12-Jan-2007 12-Nov-2007
Document revision history
Revision 0.1 1 2 Initial release. Document status promoted to Full Datasheet. Small text changes. Applied Numonyx branding. Changes
21/22
M36W0R6050T1, M36W0R6050B1
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 11/5/7, Numonyx, B.V., All Rights Reserved.
22/22

▲Up To Search▲

Price & Availability of M36W0R6050B1

	To Download M36W0R6050B1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .